The present invention relates to timing circuits, and more particularly to a phase-selectable flip-flop which allows selecting one of two sampling times, either on the rising or the falling edge of a clock pulse.
Due to the setup and hold time of latches and flip-flops there is a brief period when there is uncertainty in the transfer of data through such devices. This period is referred to as a metastable region. Where a data input is sampled using a four-phase login circuit, at high clock frequencies on the order of 500 MHz the uncertainty of delay in the data output from each phase is of sufficient duration with respect to the sample clock period that there is no one point at which all four phases can be clocked in order to output them simultaneously on a single clock phase without violating a setup/hold time. Yet at lower sampling rates such a simultaneous point free from uncertainty regions in all phases is attainable. What is desired is a means for inserting a delay in one or more of the phases at high frequency sampling rates to attain a simultaneous point free of uncertainty in all phases, while bypassing the delay at lower sampling rates.